A thin film transistor liquid crystal display (TFT-LCD for short) is an important flat panel display device. According to a direction of an electric field driving liquid crystal molecules, TFT-LCDs may be classified into vertical electric field type TFT-LCDs and horizontal electric field type TFT-LCDs. For a vertical electric field type TFT-LCD, a pixel electrode needs to be formed on an array substrate, and a common electrode needs to be formed on a color-filter substrate, as in the case of commonly used TN mode. For a horizontal electric field type TFT-LCD, both a pixel electrode and a common electrode need to be formed on an array substrate, as in the case of advanced super dimension switch (ADS) mode. The ADS technology is a core technology of planar electric field having wide viewing angle, and the main concept thereof is as follows: a multi-dimensional electric field is formed by an electric field generated by edges of slit electrodes in a same plane and an electric field generated between a slit electrode layer and a plate electrode layer, so as to allow all liquid crystal molecules having various orientations between the slit electrodes and right above the electrodes in a liquid crystal cell to rotate, thereby increasing both the operation efficiency of the liquid crystal molecules and the light transmittance thereof. The ADS technology can improve the picture quality of a TFT-LCD product, and has advantages such as high resolution, high light transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, no push Mura, and the like. For various applications, technologies such as a high light transmittance ADS (I-ADS) technology, a high aperture ratio ADS (H-ADS) technology, a high resolution ADS (S-ADS) technology, and the like have been developed as improvements on the ADS technology.
An I-ADS mode array substrate is described below in conjunction with the following manufacturing method.
Step 1 includes: forming a first transparent conductive layer on a substrate, and forming a pattern including a pixel electrode (a plate electrode) by a patterning process.
Step 2 includes: forming a gate metal film on the substrate subjected to the above step, and forming a pattern including a gate of a thin film transistor by a patterning process.
Step 3 includes: forming a gate insulating layer on the substrate subjected to the above steps.
Step 4 includes: forming an active-layer film on the substrate subjected to the above steps, and forming a pattern including an active layer by a patterning process.
Step 5 includes: forming a source-drain metal film on the substrate subjected to the above steps, and forming a pattern including a source and a drain by a patterning process.
Step 6 includes: forming a passivation layer on the substrate subjected to the above steps, and forming a pattern including a main via penetrating through the passivation layer and the gate insulating layer by a patterning process.
Step 7 includes: forming a second transparent conductive layer on the substrate subjected to the above steps, and forming, by a patterning process, a connection electrode which connects the drain to the pixel electrode through the main via, and forming a common electrode (a slit electrode) by a patterning process.
The inventors of the present invention found that at least the following problem exists in the prior art: since a dry etching process is commonly used for forming the main via in the step 6, the source-drain metal film will not be etched, whereas the active layer will be etched due to that its material is generally polysilicon, amorphous silicon, or the like, resulting in a problem of undercut occurring under the drain. It is apparent that, due to the phenomenon of undercut occurring under the drain, the second transparent conductive layer formed subsequently tends to break at a position where the undercut occurs.